1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit, and is applied to, for example, a PLL circuit driven by a power-supply voltage supplied from a voltage regulator.
2. Description of the Related Art
A PLL circuit, which outputs a signal at an integral multiple of the frequency of an input signal to generate a high-speed clock for an IC (Integrated Circuit) chip such as LSI and DSP (Digital Signal Processor), is widely used.
The PLL circuit is used to convert an externally inputted reference clock with a voltage controlled oscillator (herein referred to as VCO) and thereby to output the converted clock as a predetermined output clock. For example, Japanese Patent Application Publication No. 2004-112157 describes the VCO which is driven by a power-supply voltage supplied from a voltage regulator or the like. The voltage regulator is provided for reducing the change in a driving voltage for the VCO even when an external power-supply voltage is changed.
The oscillation frequency of the VCO is proportional to a control voltage (Vctrl) applied to a control terminal, and to a driving voltage (VRe) supplied from a regulator or the like.
How much the oscillation frequency is changed when the control voltage (Vctrl) is changed by a unit voltage, is generally called KVCO. When the KVCO is large, a slight change in the control voltage (Vctrl) causes the frequency of the output clock of the VCO to be changed. The change in frequency is nothing but the change in phase. Accordingly, a jitter is increased. It is desirable that the jitter be reduced as much as possible.
In the meanwhile, the frequency of the reference clock externally inputted to the PLL circuit is changed in some case when the power is supplied on or in a predetermined test mode. In this case, the band width of the operating frequency range (fVCO) of the PLL circuit needs to be increased in response to the above change. Nonetheless, in order to increase the band width of the operating frequency range (fVCO), the KVCO which is equivalent to the gradient of the operating frequency range (fVCO) theoretically needs to be increased. On the other hand, when the KVCO is increased, a jitter is consequently increased as described above. Thus, it is generally a conflicting requirement to reduce the jitter and to increase the band width of the operating frequency of the PLL circuit at the same time.
In addition, according to the above relationship, the oscillation frequency of the VCO increases with the increase in the driving voltage (VRe), and decreases with the decrease in the driving voltage (VRe).
Accordingly, when the output voltage (VRe) of the voltage regulator or the like is changed due to a variation in the production process, the characteristic line of the oscillation frequency is shifted up or down. This results in a problem that an oscillation frequency range (operating frequency range) to be guaranteed is consequently narrowed, in considering the change in the oscillation frequency due to the variation in the production process for the voltage regulator or the like.
As described above, the conventional PLL circuit has a problem that the oscillation frequency range cannot be expanded while the jitter is kept low.
In considering the amount of change in the output voltage (VRe) supplied from the voltage regulator due to the variation in the production process, the guaranteed usable range of the output voltage from the voltage regulator is to be limited, also resulting in a problem of the narrowed oscillation frequency range (operating frequency range) of the VCO.